With continuing advances in the semiconductor industry, electrical circuits are often designed to utilize as little space as is practicable. Circuit space often is a valuable asset which needs to be conserved, and a miniaturization of electrical circuits often improves speed, reduces noise and leads to other performance advantages. In combination with the need to conserve circuit space, circuit interconnections should be designed to function reliably under the expected operating condition.
Vias are often utilized with integrated circuits (IC) to provide the interconnection necessary between the internal circuitry of the IC and the external interface, for example circuitry printed wiring board electronic modules. This interconnection can be achieved in two ways. With the first approach, the vias are finished with metal pads which are wirebonded to lead frames. The back or inactive side of the semiconductor device is metallized so that the device can be soldered to a heat-spreader for heat dissipation, if needed. The complete device is then molded in a plastics package. The lead frames, which extend from inside of the plastics package to the outside of the package, are to be soldered to the printed wiring board (PWB) during assembly. However, the wire-bonding method is a major contributor to signal parasitic inductance, especially if the wire loop length is not strictly minimized. Such parasitic inductance distorts signal frequencies.
The second approach, commonly referred to as "flip chip", is to have a suitable layered metallization, using conventional metal deposition processes for the via bond pad, upon which a metal bump is constructed, and the device can be bonded directly to the substrate through the bump. Flip chip or direct chip attachment mounting techniques are used to increase the density of electrical circuits. Flip chip mounting techniques relate to "flipping" the die over and directly attaching the active or top surface of the semiconductor device to a printed wiring board. Since the actual semiconductor die size is so much smaller than a typical semiconductor package, there is significant savings with integrated circuit space and substrate space. This method saves substantial packaging costs, integrated circuit space and substrate space.
Flip chip technology uses electrically conducted bumps such as tin-lead solder or gold, to provide input/output interconnects between the circuit on the silicon chip and the circuitry on the substrate of an electronic module. The basic connection scheme consists of die input/output (I/O) pads that have had bumps applied, plus a matching set of substrate solder wettable pads. The die I/O pads are formed by etching vias through the passivation layer followed by hermetically sealing the via by evaporating layers of the appropriate materials through a mask. A solder alloy is then deposited on the pad to form the solder bump. Meanwhile, the substrate solder wettable pads are formed to interconnect with the bumps on the integrated circuit, for example through reflow. A flux is used to remove oxides on metal surfaces in order to promote sound metallurgical bonding. The reflow step can be achieved in a vapor-phase or infrared oven or by a localized heat source. The use of flip chips on printed wiring boards (PWB) is desirable due to its simplicity, low cost, high density and reliability.
However, conventional flip chip techniques have several disadvantages. One significant problem is that direct attachment of a device to a printed wiring board provides little opportunity for relative movement between the device and the printed wiring board. Traditional printed wiring boards are made using a substrate, such as a glass fiber reinforced epoxy or a polyamide, which has a vastly different coefficient of thermal expansion than the silicon from which most semiconductor devices are made. Consequently, when the electrical circuit experiences temperature changes, the printed wiring board expands at a different rate than the semiconductor device. As a result of the stresses experienced from the differing coefficient of thermal expansion, a solder joint may break, causing failure of the electronic product.
Yet another problem associated with conventional flip chip techniques is that of metallurgical incompatibilities between semiconductor devices and printed wiring boards. Semiconductor devices typically incorporate aluminum bonding pads, which are easier to deposit and are suitable for metal bonding purposes. However, the aluminum pads are not solderable with the tin-lead solders. Consequently, flip chip techniques first ensure that pad geometries of a semiconductor device are compatible with the printed wiring board, then deposit a barrier metal over the pads, followed by a copper layer over the barrier metal. The barrier metal protects the aluminum device pad from the copper. Bumps are formed over the copper layer for interconnection with the printed wiring board. Conventional flip chips use tin-lead solders to form the bumps. However, with solder bumps, there needs to be certain distances between the bumps in order to avoid bridging between the bumps during reflow soldering, therefore limiting the input/output density or "pitch" of the device. In order to satisfy the need for high density electronic packaging, gold bumps have been used for interconnection to tin over the copper pad on the PWB through thermocompression bonding. However, gold is very expensive and therefore limits the wide application of such products. Accordingly, there is a need for a reliable flip chip bump interconnect which takes care of the problems associated with changing temperature conditions, is capable of providing high density fine pitch interconnection, and is affordable.